Semiconductor devices often have analog signals from off chip or from an embedded analogue function that must be processed in the digital domain. Noise, glitches, or transient signal variations resulting from mechanical bounce occurring at the initiation of a change of state of the analog signals must be removed before the signal values are further processed.
Debouncing circuits and methods for removing the noise, glitches, or transient signal variations resulting from the mechanical bounce are well known in the art. A classic debouncing method is a resistor-capacitor (RC) network where a time constant of an RC network determines a hold from activation time once a switch has been activated to an open or closed state. During the initial period of the activation, the mechanical switch will “bounce” between the open and closed state until after a period of time the switch assumes the new state. To mask this period and prevent errors in the function monitoring the switch, the time constant of the RC network is chosen to be sufficiently large to be longer than the activation or deactivation period.
In digital systems, counting at a fixed frequency to a fixed value typically performs this debounce function. The count is restarted each time the signal to be debounced changes value. Only when this counter has reached a predetermined value is the (now stable) signal value allowed to pass to the output of the debounce circuit. The optimum circuit provides the required debounce functionality while keeping latency of the signal to a minimum. A digital form of a debounce circuit is described in U.S. Pat. No. 4,523,104 (Norris, et al.). The debounce circuit eliminates transient pulses generated by bouncing mechanical contacts within a switch. A shift register accepts a series of binary input signals from the switch and propagates the signal out the register in parallel to a logic device for generating a resultant binary signal corresponding to the switch's debounced signal state.
U.S. Pat. No. 5,315,539 (Hawes) describes a method and apparatus for debouncing signals. The apparatus provides lockout filters for debouncing signals that include an input part for receiving a plurality of input signals from switches, a microprocessor and an output part. The filters simultaneously process a plurality of input binary signals in parallel according to a sequence of mask values that individually adjust the filter response function for each of the individual filter channels. A multichannel filter has a filter simultaneously filtering each input signal of a plurality of input signals, the filter including a plurality of independent filter channels, each independent filter channel filtering a corresponding input signal of the plurality of input signals to produce a corresponding output signal of a plurality of output signals. The multichannel filter also has a mechanism for independently adjusting a filter response time of each independent filter channel.
FIG. 1 is a schematic diagram of a debounce circuit of the prior art. The data 10 is a signal that originates from a mechanical or analog circuit source that may contain noise, glitches, or the transient signal variations resulting from the mechanical bounce particularly at the beginning of a change from one particular state to at second state. In the case of a mechanical switch, the switch maybe opening or closing. During this initiation of a new state, the switch may make and break contact for a number of times. In some instances, the time that the mechanical or analog circuit source changes from the first state to the second state may be sufficiently slow that the input circuitry provides much apparent logic hash or oscillations resulting from the analog signals remaining in illegal logic regions of the receiving circuitry for a long time duration.
The data 10 is applied to the D-type Flip-Flops 15 and 20 to eliminate some of the logic hash or oscillations between the clock CK pulses. The data having any or all of the logic hash or oscillations removed is applied to an edge detector 25. The edge detector consists of a third D-type Flip Flop 27 that receives the data from the output of the second D-type Flip-Flop 20 and applies it to the exclusive OR circuit 29. The other input of the exclusive OR circuit 29 is the output of the D-type Flip-Flop 20. The output of the third D-type Flip Flop 27 delays the data output of the output of the second D-type Flip-Flop 20 by one clock CK cycle. The exclusive OR circuit 29 determines if the outputs of the second D-type Flip-Flop 20 and the third D-type Flip Flop 27 are not equal. If the outputs of the second D-type Flip-Flop 20 and the third D-type Flip Flop 27 are not equal, the count/reset output 30 of the exclusive OR circuit 29 is turned on causing the N-bit counter 35 to be reset and start counting from it starting value. The clock 40 increments the counter and the count output 45 of the N-bit counter 35 contains the current count value. The count output 45 is applied to the threshold comparator 55 to be compared with the threshold value 50. When the count value 45 is less than the threshold value 50 the output of the threshold comparator 55 is at a state (0) indicating that the count value 45 is less than the threshold value 50. When the count value 45 is equal to or greater than the threshold value 50, the output of the comparator 55 is at a state (1) indicating this. The output of the comparator 55 is applied to the select gate of the selector 60. When the count value 45 is less than the threshold value 50, the output data 70 from the fourth D-type Flip Flop 65 is fed back to the first input (0) of the selector 60 that is then applied to the fourth D-type Flip Flop 65 to maintain the debounced data output 70 of the fourth D-type Flip Flop 65 at the original level of the data prior to the detection of the transition edge. When the count value 45 is equal to or greater than the threshold value 50, the output from the comparator 55 applied to the selector 60 sets the selector 60 to transfer the signal from the second input (1) to the output of the selector 60. When the time determined by the N-bit counter 35 has elapsed after the last bounce detected by the edge detector 25, the data at the output of the second D-type flip flop 20 is transferred to the data input D of the fourth D-type Flip Flop 65 and thence to the debounced data output 70.
The source of the input data signal 10 may vary depending on the application, user requirements or environment. It is desirable to be able to change the debounce duration within a circuit application dynamically. Being able to support both a long and a short debounce time with the same circuit running at a fixed rate, would require that the number of bits of the N-bit counter 35 be constructed to support the longest debounce duration. This results in redundant, unused circuitry whenever the long debounce setting is not used.